Synopsys Front End and Back End University Bundle
Synopsys Front End and Back End University Bundle includes a wide range of tools for verification and synthesis of digital designs for ASICs & FPGAs targets. Front End Bundle includes RTL ASIC Synthesis (Verilog, SystemVerilog and VHDL), high level synthesis (C/C++), FPGA Synthesis and Multi-FPGA partitioning, test insertion and ATPG, logic simulation (VHDL, Verilog, SystemC, SystemVerilog, and SVA), logical equivalence checking, signoff timing analysis (with signal integrity), signoff power analysis, multi-voltage simulation, multi-voltage structural checking, and fast spice simulation. The back end bundle includes tools for Physical implementation (Floorplanning, Placement, CTS, Routing, and Optimisation), RC extraction, DRC, LVS, Signoff Rail analysis.
Synopsys Full Custom University Bundle
Synopsys Full Custom University Bundle includes a wide range of tools for full-custom design, analogue circuit simulation and verification. It includes for full custom design: Schematic capture, Schematic driven layout, Spice and Fast-Spice and RF simulation, and simulation analysis and debug.
Synopsys TCAD Suite (2D/Advanced)
Synopsys TCAD Bundle provides an extensive set of tools for semiconductor process and device modelling, with an integrated analysis scenario exploration environment. The Advanced TCAD Bundle includes tools for 2D/3D process simulation and modelling, structure definition, device simulation, compact model generation, and 2D/3D interconnect field solvers.
